1.7. SINANO Workshop: "Nanowires for Logic, Memory and New Functionalities",

Organizer: Francis Balestra, Sinano Institute - Grenoble INP/CNRS

Date of the Workshop: September 20, 2013, Bucharest, Romania - during ESSDERC-ESSCIRC’2013

Abstract: This Workshop is supported by the European Institute of Nanoelectronics SINANO (www.sinano.eu) and aims at discussing state‐of‐the art results and disruptive achievements in the field of Nanowires for very low power and high performance logic and memory, and for adding new functionalities to CMOS in the More than Moore domain (sensing, energy harvesting, RF and e-cooling).


Friday, September 20th, 2013 (8:50-15:30)

-8:50 "Introduction", Francis Balestra, Sinano Institute
-9:00 "Nanowire devices for the 10nm technology node and beyond", Sylvain Barraud, CEA-LETI -9:30 "Extending Moore’s law: Nanowires to the rescue", Nadine Collaert, IMEC
-10:00 "Energy efficient electronics: prospects and challenges of superlattice nanowire FETs", Elena Gnani, Giorgio Baccarani, IUNET-University of Bologna

-10:30 Coffee break

-11:00 "Complementary Strained Si nanowire TFETs and Inverters", Qing-Tai Zhao, Siegfried Mantl, Forschungszentrum Juelich
-11:30 "Challenges and opportunities in InAs Tunnel FETs: a simulation study", Marco Pala, IMEP-LAHC, Grenoble INP/CNRS, David Esseni, IUNET-University of Udine

-12:00-13:30: Buffet lunch

-13:30 "Nanowires for sensing applications", Per-Erik Hellström, Mikael Ostling, KTH
-14:00 "Piezoelectric nanowires for mechanical energy harvesting ", Gustavo Ardila, IMEP-LAHC, Grenoble INP-Minatec
-14:30 "Nanowires and nanostructured Si for RF applications", Androula Nassiopoulou, IMEL/NCSR Demokritos
-15:00 "e-cooling and impact of low dimensionality", Evan Parker, David Leadley, University of Warwick

15:30 End of Workshop