Short biography: Witold (Witek) P. Maszara has received MS degree in Electronics from Technical University of Wroclaw, Poland, and PhD degree from University of Kentucky in EE. Co-author of 100+ papers, author of over 50 invited talks and seminars, and over 60 patents in the field of microelectronics. Served as Technical Program Chair and General Chair of IEEE International SOI Conference, Chair of IEEE IEDM’s Subcommittee for Integrated Circuits and Manufacturing . Currently serving on technical committees for IEDM and VLSI Symposium on Technology. Member of advisory boards for Semiconductor Research Corporation, Sematech, National Science Foundation, IMEC (Belgium) and INMP (Stanford U.) for broad range of semiconductor technology programs. Current areas of interest: CMOS logic technology, dense embedded memory and integrated photonics for deep submicron CMOS applications. He is presently employed at GLOBALFOUNDRIES as Principal Member of Technical Staff. Currently manages GLOBALFOUNDRIES Exploratory Research for 7nm technology node and beyond, covering Device, Interconnect, Memory and Photonics research.

Title: FinFETs: Technology and Circuit Design Challenges

Abstract: It took quarter of a century for multi-gate transistor to make it from first demonstration in research to a product – 22nm technology node microprocessor in 2012. FinFETs offer superior performance over incumbent planar devices due to their significantly improved electrostatics. FinFET technology faced two key barriers to their implementation in products: demanding process integration and its significant impact on layout and circuit design methodology. In this paper we focus on challenges and tradeoffs in both of these areas. Fin shape, pitch, isolation, doping, crystallographic orientation and stressing as well as device parasitics, performance and patterning approaches will be discussed. Implementation of high mobility materials for finFET devices will also be briefly reviewed as well as design challenges for logic and SRAM circuits.